Dr. Donald G. Pierce, Ph.D.
Printable Word Document

1224 Hiawatha Drive NE
Albuquerque, NM  87112
(505) 610-2476
DPierceST@aol.com

Donald G. Pierce received the B.S., M.S. and Ph.D. in Physics from Rensselaer Polytechnic Institute.  During much of the '80's he was an Associate at Booz, Allen & Hamilton where he conducted research on electrical overstress effects on semiconductor devices, including electrostatic discharge.  Dr. Pierce was then employed as a Senior Member of the Technical Staff at Sandia National Laboratories' Reliability Physics Department where his research focus was on electromigration in metal interconnects and techniques for establishing the overall reliability of microelectronics.  Dr. Pierce is currently President and a founder of Sandia Technologies Inc., which provides wafer level reliability techniques world-wide industry in partnership with Agilent Technologies.  He is a senior member of the IEEE, Life Member and past-President of the Electrostatic Discharge Association, a past-General Chair of the EOS/ESD Symposium and was the U.S. editor of the journal Microelectronics Reliability.

Professional and Scientific/Engineering Societies

Donald G. Pierce

Electrostatic Discharge (ESD) Association

The ESD Association (formerly the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Association) is a 2,000 member international professional/technical society founded in 1983 and headquartered in Rome, NY.  The goal of the association is to advance the theory and practice of electrostatic discharge (ESD) avoidance and mitigation of ESD and other electrical overstress effects on electronics.  To achieve those goals the ESD Association conducts an annual symposium and tutorial, conducts tutorials at local chapters across the country, develops and writes standards for use by industry and government (and is an American National Standards Institute (ANSI) affiliate), maintains 6 local chapters across the U.S., awards educational grants to U.S. and foreign universities, awards an Outstanding Contributions Award in the Field and is developing a professional certification program.
Member since 1983

Treasurer 1998 - 2000

Awards Chairman 1996 - 2000

President 1994 – 1995
Under my stewardship, the association launched a professional certification program, revamped our financial tracking system, revised our local chapter affiliation program and expanded our field of interest to non-electronics areas.

Sr. Vice President 1992-1993
As Sr. Vice President was responsible for the Headquarters operation in Rome, NY.  I set office policy and prepared budgets, staff performance reviews and salary recommendations.  Lead the headquarters operation through a difficult period including the resignation of one office manager and the untimely death of another office manager.

Vice President 1990-1991
Main contributions in Strategic Planning below.

Elected member of the Board of Directors - 1985-2000
The Board of Directors (formerly the Administrative Committee) of the ESD Association consists of twelve members, elected by the membership, and the officers of the association.  The Board is responsible for setting association policy and budget and approving all association activities including standards.

Chairman, Strategic Planning Committee 1990-1991
Proposed and executed the transition from dual (with the IIT Research Institute) to single sponsorship of the EOS/ESD symposium.  Developed a strategic plan whose elements were implemented including regional tutorials, development of standardized lecture materials and development of a professional certification program.

Chairman, Tutorial Committee 1989
Planned and executed an 8 session tutorial that drew 250 attendees.

Vice Chairman, Device Testing Standards Committee - 1987

Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium

The EOS/ESD Symposium is a technical conference held annually since 1979.  The symposium is sponsored by the ESD Association in cooperation with the IEEE.  The symposium and associated exhibition typically draws in excess of 1,000 attendees and exhibitors from all over the world.  The technical sessions span a wide range of topics related to electrical overstress and electrostatic discharge including the physics of failure, on-chip protection design, test methods, system level effects, ESD suppressive materials and ESD control measures and training.  In conjunction with the symposium are a 120 booth exhibits area, workshops, tutorials and seminars.

Member of Board of Directors 1988 – 1996
The Board of Directors of the EOS/ESD Symposium consisted of the past nine General Chairpersons, the current chair of the symposium and the ESD Association president.  The Board of Directors was responsible for setting overall policy and providing strategic planning for the symposium.

Chairman of Board of Directors 1989 & 1990
Under my stewardship executed the transition from dual (with the IIT Research Institute) to single sponsorship of the symposium.  Restructured the make-up of the Board and proposed and passed a new charter for the board.

Symposium General Chair – 1988
The General Chair is responsible for leading the Steering Committee and the planning and implementation of that year's symposium.  Under my leadership, the 1988 symposium held in Anaheim, CA set the attendance record and the record, at that time, for the financial return to the sponsors.

Symposium Vice General Chairman – 1987
Assisted the 1988 General Chair in planning that symposium and selected the 1986 papers to receive the Best Presentation and Best Paper Awards.

Technical Program Chair – 1986
Led the 25 member Technical Program Committee in paper solicitation and selection and planning and implementing the technical program for the 1986 symposium.  Introduced the use of laptop computers and overhead data display to aid in paper selection.

Technical Program Vice Chair – 1985
Assisted the 1985 Technical Program Chair in defining the technical program.

Member Technical Program Committee 1984 - Present

Session Moderator, 1983 & 1985
Moderated and coordinated sessions on the physics of failure and modeling.

Other Professional Activities

U.S. Editor, Microelectronics Reliability, 1997 and 1998.

Technical Program Committee - Integrated Reliability Workshop, 1993 and 1994. 
The Integrated Reliability Workshop is held annually at the Stanford Sierra Lodge and provides 3 days of intense interaction with workers in the field of reliability of integrated circuits.  Topics include wafer-level reliability, known good die, building in reliability and reliability of multi-chip modules.

Reviewer for IEEE Transactions on Electron Devices in the areas of electrostatic discharge and electromigration.

Reviewer for IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems in the area of electrostatic discharge.

Reviewer for the Journal of Electrostatics in the area of electrostatic discharge.

Member of the Technical Program Committee and session Co-Chair for the 1989 Government Microelectronics Applications Conference (GOMAC)

Member of JEDEC JC-40.2 Task Group, 1986-87.
The JC-40.2 was chartered to develop a new standard for testing integrated circuits to the ESD Human Body Model.  Because of restrictions in working under the JEDEC umbrella, the group disbanded and reformed under the auspices of the ESD Association.

Publications List

Donald G. Pierce

1.   D.G. Pierce, J. Educato, V. Rana. and D. Yost, "Wafer-Level Electromigration Applied to Advanced Copper/low-k Dielectric Process Sequence Integration," Proceedings 1998 IEEE Integrated Reliability Workshop.

2.   D.G. Pierce and P.G. Brusius, "Electromigration - A Review," Microelectronics and  Reliability, vol. 37, no. 7, pp. 1053-1072,  July 1997.

3.   D.G. Pierce, E.S. Snyder, S.E. Swanson, and L.W. Irwin, "Wafer-Level Pulsed-DC Electromigration Response at Very High Frequencies," Proceedings of the 1993 International Reliability Physics Symposium, March 1994, pp. 198-206.

4.   E.S. Snyder. D.G. Pierce, D.V. Campbell and S.E. Swanson, "Self-Stressing Structures for Electromigration to 500 MHz," Proceedings 1994 IEEE International Test Conference, March 1994.  (Best Paper winner).

5.   E.S. Snyder, D.V. Campbell, S.E. Swanson, and D.G. Pierce, "Novel Self-Stressing Test Structures for Realistic High Frequency Reliability Characterization."  Proceedings of the 1993 International Reliability Physics Symposium, March 1993, pp. 57-65.  (Best Paper Winner).

6.   D.G. Pierce and P.G. Brusius, "Correlation Between Highly and Moderately Accelerated Electromigration Tests," IEEE Elect. Dev. Let., Vol. 14, No. 6, June 1993.

7.   T.A. Dellin, W.M. Miller, D.G. Pierce and E.S. Snyder, "Wafer Level Reliability (Invited Paper)," Proceedings of SPIE Microelectronics Manufacturing and Reliability, Vol. 1802,  Sept. 1992.

8.   D.G. Pierce, "A Temperature Dependent SPICE Macro-Model for Power MOSFETs,"  Proceedings of the IEEE Midwest Symposium on Circuits and Systems," May, 1991,  pp. 597-601.

9.   D.G. Pierce, W.L Shiley, B.D. Mulcahey, K.E. Wagner, and M. Wunder, "Electrical Overstress Tasting of a 256K UVEPROM to Rectangular and Double Exponential Pulses," Proceedings of the 1988 Electrical Overstress/Electrostatic Discharge Symposium, EOS-10, Sept. 1988, pp. 137-146.

10. D.G. Pierce, "Critical Issues Regarding ESD Sensitivity Classification Testing," Proceedings of the 1987 Electrical Overstress/Electrostatic Discharge Symposium, EOS-9, Sept. 1987, pp. 51-58.

11. D.G. Pierce, "Electro-Thermomigration as an Electrical Overstress Failure Mechanism," Proceedings of the 1985 Electrical Overstress/Electrostatic Discharge Symposium, EOS-7, Sept. 1985, pp. 67-76. (Best Paper Winner).

12. D.G. Pierce, J. Perrilat Jr. and W.L. Shiley, "An Evaluation of EOS Failure Models," Proceedings of the 1984 Electrical Overstress/Electrostatic Discharge Symposium, EOS-6, Sept. 1984. pp. 44-56.

13. D.G. Pierce, "Modeling Metallization Burnout in Integrated Circuits," Proceedings of the 1982 Electrical Overstress/Electrostatic Discharge Symposium, EOS-4, Sept. 1982, pp. 56-61.

14. D.G. Pierce and R.M. Mason Jr., "A Probabilistic Estimator for Bounding Transistor Emitter-Base Junction Transient-Induced Failures" Proceedings of the 1982 Electrical Overstress/Electrostatic Discharge Symposium, EOS-4, Sept. 1982, pp. 82-90.

15. D.G. Pierce and R.M. Mason, Jr., "The Characterization of Transistor Electrical Overstress Failure Probability Density Functions," IEEE Trans. Nuc. Sci., Vol. NS-29, No. 6, Dec. 1982, pp. 1452-1458.

16. D.G. Pierce and D.L. Durgin, "An Overview of Electrical Overstress Effects on Semiconductor Devices" Proceedings of the 1981 Electrical Overstress/Electrostatic Discharge Symposium, EOS-3, Sept. 1981, pp. 20-31.

17. D.G. Pierce and H.B. Huntington, "Thermomigration of Ni in Pb," Bulletin of the American Physical Society, March 1980.

18. D.G. Pierce and R.A. Levy, "Perspective on Small, Flat Video Displays," IEEE Trans. Cons, Elect., Vol. CE-24, No. 4, November, 1978.

19. D.G. Pierce, "Can Charged Boards Cause IC Failure?," EOS/ESD Technology Magazine, February/March, 1988, pp. 7-8.

Invited Tutorials

D.G. Pierce, "Electrostatic Calculations for the ESD Engineer," presented at the 1998-2001 EOS/ESD Symposium, October, 1998-2001, 85 pages.

D.G. Pierce, "EOS/ESD Failure Mechanisms and Models," presented at the 1998-2001 EOS/ESD Symposium, October, 1998-2001, 80 pages. 

D.G. Pierce, "EOS/ESD Failure Mechanisms and Models," presented at the 1997 EOS/ESD Symposium, October, 1997, 57 pages. 

D.G. Pierce and E.S. Snyder, "Wafer Level Reliability — Pushing the Envelope," presented at the 1997 IEEE International Reliability Physics Symposium, April, 1997,31 pages. 

D.G. Pierce, "ESD Failure Mechanisms," presented at the 1996 EOS/ESD Symposium, September, 1996, 57 pages. 

D.G. Pierce, "ESD Failure Mechanisms," presented at the 1996 EOS/ESD Symposium, September, 1995, 52 pages.

D.G. Pierce, "Electrostatic Discharge (ESD) Failure Mechanisms," presented at the 1995 IEEE International Reliability Physics Symposium, April, 1995, 53 pages.

D.G. Pierce, "Wafer Level Electromigration Testing," presented at the 1993 Integrated Reliability Workshop," October 24, 1993, 22 pages.

D.G. Pierce, "Physics of Failure and Analysis," presented at the 1993 EOS/ESD Symposium, September, 1993, 85 pages.

D.G. Pierce, "Failure Mechanisms and Modeling," presented at the 1991 EOS/ESD Symposium, September, 1991, 84 pages.

D.G. Pierce, "Advanced ESD and Modeling," presented at the 1990 EOS/ESD Symposium, September, 1990, 73 pages.

D.L. Durgin and D.G. Pierce, "Electromagnetic Pulse (EMP) Effects on Electronic Components and Equipment, "Tutorial Short Course" presented at 1983 IEEE Nuclear Space and Radiation Effects Conference, July 17, 1983, 67 pages.